1. Field
This disclosure relates generally to semiconductor device packaging, and more specifically, to providing sufficient input/output contacts on small form-factor packages.
2. Related Art
Smaller electronic devices and demands for increased functionality of electronic circuits in the same space create the need for near chip scale packages. One type of near chip scale package is the flat no-leads package, such as dual-flat no-leads (DFN) and quad-flat no-leads (QFN) packages. Flat no-leads packages provide a semiconductor device encapsulated in a molding material and coupled to the input/output contacts, or lands, on the perimeter of the device package through a lead frame substrate.
Continued demands for smaller package footprints have resulted in decreasing package sizes, in some cases to 2 mm×2 mm or less. At these scales, contact pitch limitations restrict the number of contacts that can be provided along the perimeter of the package. In addition, demand for increased functionality in these small packages makes it desirable for larger semiconductor devices to be incorporated in the package. But traditional flat no-leads packaging techniques require wire bonding of die contacts to the lead frame, which takes up space within the package. Further, this increased functionality often requires additional input/output contacts that cannot be provided along the perimeter of traditional small flat no-leads packages. In addition, the traditional techniques of forming the flat no-leads packages can be resource and time intensive due to repeated mechanical processes, such as performing wire bonding.
It is therefore desirable to provide a small, near chip scale package that can provide increased numbers of input/output contacts, while at the same time providing capacity for larger semiconductor devices in the same package footprint.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.